// counter.v

`timescale 1ns / 1ps
`default_nettype none

module counter
(
    input  wire       clk,
    output wire [5:0] o
);
    reg [5:0] oreg=0;
    always @ (posedge clk) begin
        oreg <= oreg+1;
    end
    assign o = oreg;
endmodule