// counter_tb.v

`timescale 1ns / 1ps
`default_nettype none

module counter_tb;
    // Inputs for counter
    reg        clk=0;
    // Outputs of counter
    wire [5:0] o;

    // Instantiate the Unit Under Test (UUT)
    counter uut
    (
        .clk(clk),
        .o(o)
    );

   integer i=0;
   initial begin
	#100;  // Wait 100 ns for simulator reset to finish
	for (i=0; i<100; i=i+1) begin
	    #100;  // Wait 100 ns, jiggle the clock, and wait another 100 ns
            clk = 1;
	    #100;
            clk = 0;
	end
	$finish;
    end
endmodule