// decoder.v

`timescale 1ns / 1ps
`default_nettype none

module decoder
(
    input  wire       e1, e2, e3,
    input  wire [2:0] a,
    output wire [7:0] o
);
    // Selected output is HIGH if E3 & not E2 & not E1; else LOW
    wire e = e3 & ~e2 & ~e1;
    // Drive selected output to 'e'; others to LOW
    assign o[0] = (a==0 ? e : 0);
    assign o[1] = (a==1 ? e : 0);
    assign o[2] = (a==2 ? e : 0);
    assign o[3] = (a==3 ? e : 0);
    assign o[4] = (a==4 ? e : 0);
    assign o[5] = (a==5 ? e : 0);
    assign o[6] = (a==6 ? e : 0);
    assign o[7] = (a==7 ? e : 0);
    // Note that I made the outputs active high here,
    // whereas the 74LS138 outputs are active low
endmodule