// decoder_tb.v

`timescale 1ns / 1ps
`default_nettype none

module decoder_tb;
    // Inputs for decoder
    reg  [3:0] a=0;
    reg        e1=0, e2=0, e3=0;
    // Outputs of decoder
    wire [7:0] o;

    // Instantiate the Unit Under Test (UUT)
    decoder uut
    (
        .a(a), .e1(e1), .e2(e2), .e3(e3),
        .o(o)
    );

   integer i=0, j=0;
   initial begin
	#100;  // Wait 100 ns for simulator reset to finish
	for (i=0; i<8; i=i+1) begin
	    for (j=0; j<8; j=j+1) begin
		a = i;
		{e3,e2,e1} = j;
		#100;  // Wait 100 ns so that we can see output update
	    end
	end
	$finish;
    end
endmodule