// fourbit_fulladder_v1.v

`timescale 1ns / 1ps
`default_nettype none

module fourbit_fulladder_v1
(
    input  wire c0,
    input  wire a1, a2, a3, a4,
    input  wire b1, b2, b3, b4,
    output wire sum1, sum2, sum3, sum4,
    output wire c4
);
    wire c1, c2, c3;
    assign sum1 = a1^b1^c0;
    assign sum2 = a2^b2^c1;
    assign sum3 = a3^b3^c2;
    assign sum4 = a4^b4^c3;
    assign c1 = a1&b1 | a1&c0 | b1&c0;
    assign c2 = a2&b2 | a2&c1 | b2&c1;
    assign c3 = a3&b3 | a3&c2 | b3&c2;
    assign c4 = a4&b4 | a4&c3 | b4&c3;
endmodule